Starting Q1/2003, Cellular3G is supporting designers and manufacturers of 3GPP FDD W-CDMA products and systems by providing a full range of IP (Intellectual Property) for the UE baseband chip set. Cellular3G has developed these IP packages to be extremely compact and power efficient. The whole package when operating at 2Mbps full-duplex will consume less than 150mW when implemented with a 0.13 process. The gate count is also extremely low with the total for the dedicated logic coming in at less than 1 million gates. The IP now offered was designed from its conception to achieve the best power consumption and 3GPP functionality when implemented on a 0.13 chip. This targeted design (vs. a general 3GPP functionality design on an FPGA system) ensures the customers of Cellular3G benefit from a smooth conversion process, from IP to chip, while achieving the lowest power consumption associated with TopHatTM. The FPGA Development and IP System System can be provided with one or all of the IP packages for emulation of derivatives. The IP has been conveniently packaged into several self-contained units with the minimum of external interfaces. The following packages are available: (C3G-01) W-CDMA UE Digital Uplink, supporting up to 2Mbps. (C3G-02) W-CDMA UE Decoder, including Turbo and Viterbi (with Blind Format detection) decoders, de-interleavers, rate-matching, etc. (C3G-03) W-CDMA Digital Receiver including RAKE, synchronization and channel estimators and trackers. (C3G-04) Complete W-CDMA-optimized RISC subsystem, cache, tightly coupled memory, including DMA, Interrupt, bridges, etc. (C3G-05) Hardware implementation 3GPP FDD UE Security (C3G-06) Entire UMTS chip IP. All these units support the 3GPP FDD Release 99 specifications [with release 4 as an option], all data rates up to and including 2Mbps. The clock rate for all the units is 30.72MHz. The units are controlled by a standard RISC processor [running 3 times the clock rate] and a full set of software for control and test is available. All IP packages are provided with Verilog source file synthesis-ready, Verilog test files, C code (sources) of applicable drivers and PDF documentation.